Realization of ultra-low power wireless receivers is one of the key challenges in low power wireless sensor network (WSN) and wireless body area network (WBAN) applications (e.g., wireless standards IEEE 802.15.4 (ZigBee) or Bluetooth Smart) as they usually dominate the overall power consumption of the remote radio or sensor nodes. In such applications, there may be only limited energy resources available. However, it is often useful to maintain long or unlimited operation time for radio nodes. As such, low power consumption of radio receivers becomes an important requirement for their design.
Conventional quadrature receiver architecture is popular for its good sensitivity and selectivity performances. An example of this type of receivers is a direct-conversion zero-IF receiver. In such architecture, the radio frequency (RF) signal is demodulated in the complex domain, resulting in a real part (I) and an imaginary part (Q) baseband signals. Although this architecture is widely used in the wireless applications, it has a high power consumption as it requires two independent RF-to-analogue signal processing circuits (commonly referred to as processing paths) for the separate demodulation of the I and Q signals, each of them including a mixer, a low-pass filter (LPF), an ADC and local oscillator (LO) buffers. Furthermore, the mismatch between I and Q signal paths (e.g., gain and delay mismatches of the low-pass filters or the programmable gain amplifier) degrades dramatically the demodulation quality. These architectures are also sensitive to presence of a DC offset voltage in the analogue baseband as it can easily saturate the ADC after amplification by the gain amplifier. Therefore, a DC offset cancellation mechanism, either AC-coupling or servo-loop, may be used in the quadrature receiver. Additionally, as the quadrature receiver operates in voltage domain, operating at low supply voltages becomes an issue, especially at the end of the analogue baseband path (i.e. at the ADC stage where the conversion of analogue voltage into digital code occurs), as lowering the supply voltage causes significant degradation of the ADC's dynamic range and hence of the dynamic range of the receiver itself.
Another disadvantage of the conventional architectures is that their overall performance is highly dependent on the performance of its analogue circuitry which degrades with CMOS technology scaling. The analogue performances of the deep-submicron CMOS devices, for example, output impedance, linearity, bandwidth, etc. are degraded significantly while the digital performances are improved.
In the paper “Ultra low power phase detector and phase-locked loop designs and their application as a receiver” (Li et al., Microelectronic Journal, vol. 42, pp. 358-364, 2011) a single path direct-conversion zero-IF receiver is described. Here, the RF signal is directly demodulated to baseband frequency (zero-frequency) by a phase-locked loop.